Design of energy efficient and reconfigurable sample rate

1.

Design of energy efficient and reconfigurable sample
rate converter using FPGA devices
Swetha Pinjerla,
Surampudi Srinivasa Rao,
Puttha Chandrasekhar Reddy

2.

Abstract
In this work an energy efficient
implementation of a FPGA architecture for a
sample rate convertor is proposed.

3.

Introduction
The goals:
To minimize area and power consumption of
multiple sample rate converter
To make perfect sync with various
communication protocols

4.

Method

5.

Specs

6.

Results and Discussion

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8.

Conclusion

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