ПОЦП_л06_2026

1. Программное обеспечение цифрового проектирования

ПРОГРАММНОЕ ОБЕСПЕЧЕНИЕ
ЦИФРОВОГО ПРОЕКТИРОВАНИЯ
БГУИР
ФАКУЛЬТЕТ КОМПЬЮТЕРНЫХ СИСТЕМ И СЕТЕЙ
КАФЕДРА ПОИТ
ВЕСНА 2026
ИВАНЮК А.А.

2.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы
…
ai {0,1}
Sequential
Logic/Scheme/Device
aN-2
aN-1
…
F0≠ ( ai, aj, ak,…)
FM-1≠ ( al, am, an,…)
Fj {0,1}
The Sequential Logic is the implementation of both Combinational logic and Memory Elements.
The output data depends not only on the input data,
but also on the previous states of the internal memory elements.
Sequential Logic
F0
F1
F2
a0
…
ME
ME
…
Combinational
Logic
…
aN-1
…
Sequential Logic
a0
a1
FM-1
The Basic Memory Element (ME)
Can store a single bit of Information.
Classification of Digital ME:
- Uncontrollable Bistable Element
- Controllable Bistable Element
- Latches
- Flip-Flops
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3.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: начало
VHDL: Bistable Scheme
Bistable Element
Bistable Scheme
INV
INV
s0
s0
U0
U1
nQ
RTL/Logic
Q
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
Entity Bistable is
Port ( Q : out std_logic;
nQ : out std_logic );
End Bistable;
Architecture Behavioral of Bistable is
signal s0, s1 : std_logic;
Begin
s0 <= not s1;
s1 <= not s0;
Q <= s0;
nQ <= s1;
End Behavioral;
Behavioral Simulation
Post-Implementation Simulation
Technological
3

4.

Bistable Element
ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: начало
6T SRAM cell
To assess SRAM cell reliability, the initial state was read multiple times after each
power-up cycle, and the statistical distribution was analyzed.
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5.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: RS-защелка
Uncontrollable
Configurable Inverter
Bistable Scheme
INV
INV
f=a’
0
s1
s0
a
RS-Latch
a
U0
f=0
U1
nQ
1
Q
Controllable
Bistable Scheme
S
R
s0
s1
Q
nQ
Mode
1
0
s0→0
s1→1
1
0
Set
0
1
s0→1
s1→0
0
1
Reset
0
0
s0→s0
s1→s1
s1
s0
Store
1
1
0
0
0
0
Undesirable
NOR2
NOR2
s0
s1
U1
U0
S
R
Q
nQ
5

6.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: RS-защелка
Controllable
RS-Latch
Bistable Scheme
S
R
s0
S1
Q
nQ
Mode
1
0
s0→0
s1→1
1
0
Set
0
1
s0→1
s1→0
0
1
Reset
0
0
s0→s0
s1→s1
s1
s0
Store
1
1
0
0
0
0
Undesirable
Possible Transaction
Forbidden Transaction
NOR2
NOR2
s0
s1
Q
U1
U0
S
nQ
R
Set
Store
Und
Reset
Set
Store
Reset
Store
Undesirable
6

7.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: RS-защелка
RS-Latch
VHDL: RS-Latch
Bistable Scheme
NOR2
NOR2
RS-Latch
s0
s1
U1
U0
S
Entity RSLATCH is
Port ( S, R : in std_logic;
Q, nQ : out std_logic );
End RSLATCH;
Architecture Behavioral of RSLATCH is
signal s0, s1 : std_logic;
Begin
P0: process ( S, s1 )
begin
s0 <= S nor s1;
end process P0;
P1: process ( R, s0 )
begin
s1 <= R nor s0;
end process P1;
Q <= s1;
nQ <= s0;
End Behavioral;
Q
nQ
R
RTL
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8.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: RS-защелка
RS-Latch
VHDL: Timing Model of an RS-Latch
Bistable Scheme
NOR2
NOR2
RS Latch
s0
s1
U1
U0
S
R
Q
nQ
…
Begin
P0: process ( S, s1 )
begin
s0 <= reject 1 ns inertial S nor s1 after 5 ns;
end process P0;
P1: process ( R, s0 )
begin
s1 <= reject 1 ns inertial R nor s0 after 5 ns;
end process P1;
Q <= transport s1 after 10 ns;
nQ <= transport s0 after 10 ns;
End Behavioral;
Metastable Oscillation
Forbidden
Transaction
8

9.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: RS-защелка
Controllable
*
Bistable Scheme
NOR2
NOR2
RS-Latch
s0
s1
U1
U0
S
Q
nQ
R
Metastable Oscillation
Forbidden
Transaction
*
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10.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: D-защелка
D Latch Always Open
VHDL: D-Latch Always Open
RS Latch
Entity DLATCH_AO is
Port ( D : in std_logic;
Q : out std_logic;
nQ : out std_logic );
End DLATCH_AO;
NOR2
NOR2
D-Latch
s0
s1
U1
U0
S
D
R
Q
nQ
Architecture Structural of DLATCH_AO is
component RSLATCH is
Port ( S : in std_logic;
R : in std_logic;
Q : out std_logic;
nQ : out std_logic );
end component;
signal nD : std_logic;
Begin
nD <= not D;
RSL: RSLATCH port map ( D, nD, Q, nQ );
End Structural;
There is no STORE mode.
It works as a buffer-repeater.
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11.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: D-защелка
D Latch
VHDL: D-Latch with Gate
RS Latch
Entity DLATCH is
Port ( D : in std_logic;
G : in std_logic;
Q : out std_logic;
nQ : out std_logic );
End DLATCH;
NOR2
NOR2
D-Latch
s0
s1
U1
U0
S
D
R
G
Q
nQ
Architecture Structural of DLATCH is
component RSLATCH is
Port ( S : in std_logic;
R : in std_logic;
Q : out std_logic;
nQ : out std_logic );
end component;
signal nD, S, R : std_logic;
Begin
nD <= not D;
S <= D and G;
R <= nD and G;
RSL: RSLATCH port map ( S, R, Q, nQ );
End Structural;
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12.

D-Latch
ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: D-защелка
RTL
Store
Reset
Store
Set
Store
12

13.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: D-защелка
D-Latch
VHDL: D-Latch with Gate
Entity DLATCH2 is
Port ( D : in std_logic;
G : in std_logic;
Q : out std_logic;
nQ : out std_logic );
End DLATCH2;
Architecture Behavioral of DLATCH2 is
signal store : std_logic;
Begin
P0: process ( D, G )
begin
if G = '1' then
store <= D;
end if;
end process P0;
Q <= store;
nQ <= not store;
End Behavioral;
RTL
Technological
VHDL: D-Latch with Gate
…
Begin
P0: process ( D, G )
begin
if G = '1' then
Q <= D;
nQ <= not D;
end if;
end process P0;
End Behavioral;
Synthesis
13

14.

D-Latch
ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: D-защелка
VHDL: D-Latch with Gate
VHDL: D-Latch with Gate
…
Begin
P0: process ( D, G )
begin
if G = '1' then
Q <= D;
nQ <= not D;
end if;
end process P0;
End Behavioral;
…
Begin
P0: process ( D, G )
begin
if G = '1' then
Q <= D;
end if;
end process P0;
The process drives two signals.
The process includes a description
of both sequential and
combinational logic.
P1: process ( D, G )
begin
if G = '1' then
nQ <= not D;
end if;
end process P1;
End Behavioral;
Equivalent
description with two
parallel processes.
RTL
As a result, two parallel latches are synthesized in
the RTL-scheme.
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15.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: D-защелка
D-Latch
Priority
CLR
PRE
G
D
Q(t-1)
Q(t)
Mode
1
X
X
X
X
0
Asynchronous Clear
0
1
X
X
X
1
Asynchronous Preset
0
0
1
d
q
d
Write d (Transparent)
0
0
0
X
q
q
Store
State Diagram
G=‘0’ or
G=‘1’ and D=‘0’
Q=‘0’
G=‘0’ or
G=‘1’ and D=‘1’
G=‘1’ and D=‘1’
CLR
D
Q
G
PRE
Si
State of Latch
Transition between states
S0
CLR=‘1’
High Priority Transition
S1
G=‘1’ and D=‘0’
Q=‘1’
CLR=‘0’
and
PRE=‘1’
Condition of Transition
Condition
Action
Action in State
15

16.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: D-защелка
Priority
VHDL: D-Latch with Gate
PRE
G
D
Q(t-1)
Q(t)
Mode
1
X
X
X
X
0
Asynchronous Clear
0
1
X
X
X
1
Asynchronous Preset
0
0
1
d
q
d
Write d (Transparent)
0
0
0
X
q
q
Store
Entity DLATCH3 is
Port ( CLR, PRE, G, D : in std_logic;
Q : out std_logic );
End DLATCH3;
Architecture Behavioral of DLATCH3 is
signal store : std_logic;
Begin
P0: process ( CLR, PRE, G, D )
begin
if CLR = '1' then
store <= '0';
elsif PRE = '1' then
store <= '1';
elsif G = '1' then
store <= D;
end if;
end process P0;
Q <= store;
End Behavioral;
Priority
D-Latch
CLR
RTL
16

17.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: D-защелка
D-Latch
VHDL: MUX3x1
Entity MUX3x1 is
Port ( A : in std_logic_vector ( 2 downto 0 );
SEL : in std_logic_vector ( 1 downto 0 );
F : out std_logic );
End MUX3x1;
Architecture Behavioral of MUX3x1 is
Begin
P0: process ( A, SEL )
begin
if SEL = "00" then
F <= A( 0 );
elsif SEL = "01" then
F <= A( 1 );
elsif SEL = "10" then
F <= A( 2 );
end if;
end process P0;
End Behavioral;
An incomplete IF statement results a LATCH
in the netlist.
Unwanted latch in
combinational logic
RTL
Unwanted latch in
combinational logic
Technological
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18.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: триггеры
Flip-Flop D-Type (DFF)
D-Latch
D
D-Latch
qm
D
D
FLIP-FLOPs
Q
CLK
G
Master
Q
qs
G
Slave
Data is latched on a 0 to 1 (rising edge)
transaction at the CLK (clock) input.
Q
VHDL: Flip-Flop
VHDL: Flip-Flop
Entity FLIPFLOP is
Port ( D : in std_logic;
CLK : in std_logic;
Q : out std_logic );
End FLIPFLOP;
Architecture Behavioral of FLIPFLOP is
signal qm, qs : std_logic;
Begin
Master: process ( CLK, D )
begin
if CLK = '0' then
qm <= D;
end if;
end process Master;
Slave: process ( CLK, qm )
begin
if CLK = '1' then
qs <= qm;
end if;
end process Slave;
Q <= qs;
End Behavioral;
Pseudostructural
VHDL Description
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19.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: D-триггер
Clock Signal (System Clock)
FLIP-FLOPs
Clock Frequency
thigh
Meander
DCLK=50%
Pulse
Width
A rising edge-triggered
D flip-flop
tlow
T=thigh+tlow
Clock Period
fCLK=1/T, Hz
Duty Cycle
DCLK= thigh /T, %
Rising
Edge
Falling
Edge
D
CLK
Q
A falling edgetriggered D flip-flop
D
CLK
Q
System Clock Sources
Oscillators
19

20.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: D-триггер
Clock Signal (System Clock)
Correct in Synthesis
FLIP-FLOPs
Popular Rising Edge Condition
…
if CLK’event and CLK=‘1’ then
…
CLK=‘1’
CLK’event
Rising
Edge
Falling
Edge
CLK=‘0’
Not correct in Simulation
A rising edge-triggered
D flip-flop
D
CLK
Q
Correct Rising Edge Condition
Rising Edge Function
…
if CLK’event and CLK=‘1’ and CLK’last_value=‘0’ then
…
…
if rising_edge( CLK ) then
…
Correct Rising Edge Condition
Falling Edge Function
…
if CLK’event and CLK=‘0’ and CLK’last_value=‘1’ then
…
…
if falling_edge( CLK ) then
…
A falling edgetriggered D flip-flop
D
CLK
Q
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21.

FLIP-FLOPs
ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: D-триггер
VHDL: D-type Flip-Flop (DFF)
Entity DFF is
Port ( CLK : in std_logic;
D : in std_logic;
Q : out std_logic );
End DFF;
Architecture Behavioral of DFF is
signal store : std_logic;
Begin
FlipFlop: process ( CLK, D )
begin
if rising_edge( CLK ) then
store <= D;
end if;
end process FlipFlop;
Q <= store;
End Behavioral;
A rising edge-triggered
D flip-flop
D
CLK
Q
RTL
Technological
21

22.

FLIP-FLOPs
ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: D-триггер
22

23.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: D-триггер
FLIP-FLOPs
VHDL: FDRE Primitive
RTL
Technological
Entity mFDRE is
Port ( R : in std_logic;
CE : in std_logic;
D : in std_logic;
C : in std_logic;
Q : out std_logic );
End mFDRE;
Architecture Behavioral of mFDRE is
signal store : std_logic;
Begin
P0: process ( R, CE, D, C )
begin
if rising_edge( C ) then
if R = '1' then
store <= '0';
elsif CE = '1' then
store <= D;
end if;
end if;
end process P0;
Q <= store;
End Behavioral;
23

24.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: RS-триггер
VHDL: RS Flip-Flop
FLIP-FLOPs
RS Flip-Flop Logic Table
R
S
CLK
Q(t-1)
Q(t)
Mode
1
X
X
0
Synchronous Reset
0
1
X
1
Synchronous Set
0
0
X
q
q
Store
The technology primitives
do not contain RS, T, or JK
flip-flops.
RTL
Technological
Entity RSFF is
Port ( R : in std_logic;
S : in std_logic;
CLK : in std_logic;
Q : out std_logic );
End RSFF;
Architecture Behavioral of RSFF is
signal store : std_logic;
Begin
P0: process ( CLK )
begin
if rising_edge( CLK ) then
if R = '1' then
store <= '0';
elsif S = '1' then
store <= '1';
end if;
end if;
end process P0;
Q <= store;
End Behavioral;
24

25.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: T-триггер
VHDL: T Flip-Flop
The technology primitives
do not contain RS, T, or JK
flip-flops.
FLIP-FLOPs
T Flip-Flop Logic Table
CLR
T
CLK
Q(t-1)
Q(t)
Mode
1
X
X
X
0
Asynchronous Clear
0
0
q
q
Store
0
1
q
q'
Toggle
RTL
Entity TFF is
Port ( CLR : in std_logic;
T
: in std_logic;
CLK : in std_logic;
Q
: out std_logic );
End TFF;
Architecture Behavioral of TFF is
signal store : std_logic;
Begin
P0: process ( CLR, CLK, store )
begin
if CLR = '1' then
store <= '0';
elsif T = '1' then
if rising_edge( CLK ) then
store <= not store;
end if;
end if;
end process P0;
Q <= store;
End Behavioral;
25

26.

ПОЦП :: Л6 :: Язык VHDL :: последовательностные схемы :: T-триггер
VHDL: T Flip-Flop (Alternative)
FLIP-FLOPs
T Flip-Flop Logic Table
CLR
T
CLK
Q(t-1)
Q(t)
Mode
1
X
X
X
0
Asynchronous Clear
0
0
q
q
Store
0
1
q
q'
Toggle
RTL
Technological
Entity TFF is
Port ( CLR : in std_logic;
T
: in std_logic;
CLK : in std_logic;
Q
: out std_logic );
End TFF;
Architecture Behavioral of TFF is
signal q_nxt, q_prev : std_logic;
Begin
q_prev <= q_nxt xor T;
P0: process ( CLR, CLK, q_prev )
begin
if CLR = '1' then
q_nxt <= '0';
elsif rising_edge( CLK ) then
q_nxt <= q_prev;
end if;
end process P0;
Q <= q_nst;
End Behavioral;
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27.

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